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Electrical and Computer Engineering

Circuits
^ An Integrated Design Methodology for Low-Power DSP and Communications Systems
I. N. Hajj,* N. R. Shanbhag,* S. Bobba
National Science Foundation, MIP-9710235

The goal of this project is to develop an integrated computer-aided design (CAD) approach for the design of low-power hardware for digital signal processing (DSP) and communications applications. The approach incorporates high-level (algorithmic) and low-level (circuit) parameters and includes novel capabilities for design exploration and low-power circuit synthesis. The design exploration will be done by developing low-power constrained algorithm design procedures that employ an analytic relation between word-level and bit-level signal statistics. The synthesis effort will incorporate signal statistics, high-level hardware models, and algorithm transformations to generate low-power dedicated implementation of DSP algorithms.

^ Composite CAD for Microelectromechanical Systems (MEMS)
S. M. Kang,* J. H. Chen
Defense Advanced Research Projects Agency, F30602-97-0328

MEMS finds many unique applications in communications systems and sensory systems. Micromechanical systems can be integrated with microelectronic systems on a common substrate. For the development of such systems, new CAD models and simulation tools are essential. In this project, new models for mechanical switches, tunable capacitors, and other core components are being developed for their use in mixed-level, mixed-signal simulation. One of the highly challenging modeling tasks is to develop a systematic nonlinear model reduction technique, especially for micromechanical systems, and this challenging problem is being addressed.

^ Domino Logic Synthesis
S. M. Kang,* K.W. Kim
Intel Corp.

CMOS domino logic has been widely used for high-speed VSLI circuits and systems. Due to the inherent nonconverting nature of domino logic, duplicate logic had to be used with significant area penalty. In this project, researchers apply implication graph theoretic approach to minimize duplicated logic by maximizing the inverter-free logic portion. For inverter elimination, automatic test pattern generation techniques are adopted. Preliminary results show as much as 30% improvement of the CMOS technology power.

^ Low-Voltage Digital CMOS Circuits
S. M. Kang,* S. M. Yoo, C. W. Kim, S. W. Jung, K. H. Baek
Semiconductor Research Corp.

State-of-the-art VLSI chips are being used in portable systems that require compactness, high speed, and long battery life. New innovative circuit design techniques are required for high speed with low power consumption. Power-minimum high-speed circuit design methods with charge recycling are being developed to drastically reduce the power consumption of low-voltage CMOS circuits. Several benchmark circuits, such as adders and multipliers, are used to demonstrate significant power savings and low leakage currents without resorting to power supply scaling, substrate biasing, or threshold voltage tuning.

^ Reliable High-Speed I/O Circuits
S. M. Kang,* J. S. Lee
L. G. Electron

In deep submicron technology, the speed and ESD reliability of I/O circuits play a critical role not only in chip-to-chip interface, but also protection of internal circuits. The conflicting requirements between high speed and high reliability must be met through rigorous analysis and innovative design concepts. Various circuit and device techniques are being investigated for high-speed VLSI chip applications. Testers have been designed, fabricated, and characterized for proof-of-concept and practical applications in close collaboration with industry.

^ Simulation and Synthesis of ESD Protection Circuits
S. M. Kang,* E. Rosenbaum,* P. Juliano, Q. Li
Semiconductor Research Corp.

The electrothermal circuit simulator iETSIM will be enhanced with the addition of an SCR model, monitoring of gate oxide voltages for prediction of gate oxide breakdown, and parameter extraction procedures for diffusion capacitances that impact protection device turn-on time. A layout extraction program ILEX will be developed to generate input decks for iETSIM. It will judiciously select for inclusion in the input deck those parasitic devices that may carry current during an ESD event. ILEX will also generate the substrate resistance network.

^ Early Interconnect Prediction
F. N. Najm,* S. Bodapati
Various gift funds

Interconnect delay is becoming dominant in deep submicron technology. Researchers are developing techniques for predicting the interconnect resources that will be required by a certain design specification. The challenge is to do this early on, before the design has been described all the way to the layout level. This is needed to help avoid the prohibitive delays associated with large interconnect networks.

^ High-Level Power Estimation in VLSI Circuits
F. N. Najm,* K. Buyukasahin
National Science Foundation, MIP 97-10235; Semiconductor Research Corp.

The high density of modern integrated circuits has led to unacceptably high levels of chip power consumption. Because of limited battery life, this presents a severe limitation in the design of portable or mobile electronics. Even in line-powered equipment, high-power chips require expensive packages and heat-sinks. Researchers are developing power estimation techniques that work at high levels of abstraction, so that the power can be estimated even before the gate-level design description is available.

^ Characterization and Optimization of Deuterium-annealed Ultrathin Dielectrics for 100 nm CMOS Applications
E. Rosenbaum,* J. Wu
Semiconductor Research Corp.

Under optimized anneal conditions, deuterium can passivate the Si/SiO2 interface and, under subsequent electron injection, the silicon-deuterium bonds are much more difficult to dissociate than the Si-H bonds formed during the conventional forming gas anneal. Detailed studies are being performed to characterize fully the hot carrier and oxide reliability of deuterium-annealed MOS transistors, to determine whether there are any interactions between the deuterium and other chemical species (such as boron) introduced during device processing, and to ascertain the role of hydrogen in gate oxide degradation. It is anticipated that deuterium annealing will allow the use of performance-driven drain engineering and perhaps of new gate dielectric materials.

^ ESD Protection Circuits for Submicron Analog and RF Integrated Circuits
E. Rosenbaum,* S. Joshi
Motorola, Inc.

Circuit level models for the ESD protection devices used in RF and analog circuits are being developed.

^ Electrostatic Discharge Protection in SOI-CMOS Circuits
E. Rosenbaum*
National Science Foundation, ECS 96-23424 CAR

Silicon-on-insulator CMOS technology holds great promise as an improved substrate for low-power, high-speed integrated circuits. However, SOI-CMOS ICs will not be produced on any large scale if they are susceptible to electrostatic discharge (ESD) induced failures. This project will answer the fundamental questions about the ESD reliability of SOI-CMOS technology. Thermal modeling, design of protection devices, and experimental testing form the basis of this investigation. Device models and stress limits developed in this research project will be implemented in a CAD tool for full-chip ESD reliability verification.

^ Electrothermal Simulation of SOI Circuits with an Emphasis on ESD Protection Circuit
E. Rosenbaum,* Y. Wang
Semiconductor Research Corp.

Researchers are developing an electrothermal circuit simulator with accurate high-current models targeted for the periphery of SOI (silicon-on-insulator) chips. Self-heating and thermal failure are particular concerns for SOI devices because the buried oxide layer impedes cooling.

^ SOI-Specific Physical Design Flow
E. Rosenbaum,* R. Kanj
Semiconductor Research Corp.

Silicon-on-Insulator (SOI) technology offers many advantages over bulk-Si CMOS such as shorter delay, smaller area, lower power, latch-up immunity, reduced substrate noise coupling, and reduced short channel effects. It is necessary to use floating-body (FB) transistors to obtain the area advantage and to maximize the speed improvement over bulk-Si. However, new design styles and guidelines are needed to take advantage of the opportunities offered by floating-body SOI devices while avoiding functional errors. Soft errors may occur in dynamic logic circuits when the floating body node gets charged up with respect to the source and the parasitic BJT turns on.

^ Substrate Noise Coupling
E. Rosenbaum,* A. Cangellaris
Motorola, Inc.

Computationally efficient methods for extracting a circuit equivalent model of the substrate from the 3d chip layout are being developed.

^ Design and Prototyping of Broadband Communications Systems
N. R. Shanbhag,* B. Chau
Analog Devices, Inc.

Adaptive equalizers are a major component of receivers in modern day communications systems. With the drive toward increasingly higher transmission rates, a corresponding increase in the complexity and therefore power dissipation and area of adaptive receivers occurs. This research focuses on the development of low-power adaptive equalizers via the application of algorithm transformation techniques.

^ Dynamic Algorithm Transformations for Low-Power Communication Systems
N. R. Shanbhag,* J. Minocha, W. Li
University of Illinois; Motorola, Inc.

The goal of this research is to develop configurable modules for signal processing and communication systems. Parametrizable modules for commonly employed blocks such as equalizer, Reed-Solomon coders and decoders, and motion-estimators are being designed. These blocks have the property that the power consumption is a function of the data and the environment. Thus, power-aware reconfigurable s ignal-processing systems can be designed via such blocks. The usefulness of the research is being demonstrated by employing it in the design of a cable modem.

^ Fundamental Bounds on VLSI Computation
N. R. Shanbhag,* R. Hegde, L. Wang
National Science Foundation, MIP 96-23737

The goal of this research is to develop an information-theoretic basis for VLSI computation so that fundamental achievable bounds on VLSI performance (such as power, area, and throughput) can be determined. Furthermore, methods to achieve these bounds are also being investigated. The usefulness of the proposed theory is being demonstrated via numerical calculations of lower bounds on power dissipation for simple static CMOS circuits as well as pipelined and parallel processing architectures.

^ Low-Power VLSI Algorithms and Architectures for DS
N. R. Shanbhag,* J. Baker, M. Goel, S. Ramprasad
Rockwell International; Samsung, Inc.

This research seeks to develop low-power equalizer architectures for digital subscriber loop applications, which includes receivers based upon a discrete multitone transmission (DMT) scheme for asymmetric digital subscriber loops (ADSL), carrierless amplitude and phase (CAP) modulation for very high-speed digital subscriber loops (VDSL), and asynchronous transfer mode (ATM) local area networks (LANs). System partitioning of functionality into programmable and dedicated processing units is being determined to achieve the lowest power. A key feature of our approach is the joint organization of algorithmic performance and power dissipation via the application of algebraic, Hilbert, and dynamic algorithm transformations.

^ Noise-Tolerant DSP in the Deep Submicron Era
N. R. Shanbhag,* R. Hegde, L. Wang, G. Balamurugan
National Science Foundation, CCR-9902745

This research addresses the design of reliable and energy-efficient DSP systems in deep submicron (DSM) SMOS technology in a unified manner via the development of noise-tolerant algorithmic and circuit design techniques. In particular, circuit design techniques that tolerate leakage, crosstalk, ground bounce, and process variations are being developed. Algorithmic approaches that exploit the statistical structure of multimedia signals to combat DSM noise are also being studied. A design methodology is being formulated that jointly applies circuit and algorithmic noise-tolerance techniques to achieve an overall level of system reliability while minimizing energy.


Summary of Engineering Research