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Electrical and Computer Engineering

Advanced Processing and Circuits
^ AlGan/GaN HFET Fabrication and Characterization
I. Adesida,* V. Kumar, A. Kuliev
Triquint Corporation

This project involves a collaboration with Triquint Corporation on the fabrication of AlGaN/GaN HFETs. Technologies for the fabrication of the HFETs will be developed.

^ Gallium Nitride Optoelectronics
I. Adesida,* L. Zhou
Defense Advanced Research Projects Agency, DAAD19-99-1-0011

This project focuses on experimental issues for the fabrication of novel optoelectronic devices and circuits in gallium nitride and related materials. UV detectors, field effect transistors, and heterojunction bipolar transistors will be investigated. Methods for integrating these devices will also be explored.

^ Porous GaN: Production, Characterization, and Applications
I. Adesida,* P. Bohn,* X. Li,* S. Kim
U.S. Office of Naval Research, N00014-01-1

This program involves the generation and characterization of porous GaN and SiC for applications in growth of high quality epitaxial layers. Matrices with dimensions down to 50 nm are to be achieved for the porous materials.

^ Processing of Gallium Nitride and Related Compounds
I. Adesida,* L. Zhou, F. Khan
ATMI/Air Force

This program consists of the development of viable processing methods for gallium nitride and related compounds. A systematic study of etching techniques, ohmic contact formation, and other metallizations will be conducted and applied to devices.

^ Resonant Enhanced Modulators
I. Adesida,* S. Rommel
Air Force; Sarnoff Corporation

This is a collaborative program with Sarnoff Corporation on resonant enhanced modulators in InP-based heterostructures. Waveguides with coupling rings are to be fabricated and characterized in InP-heterostructures. High precision patterning using inductively coupled plasma reactive ion etching and electron beam lithography will be used in fabricating the modulators.

^ Silicon Heterojunction Terabit Electronics
I. Adesida,* J. Tucker,* K. Ismail,* C. Faulkner, W. Lu, W. Lanford
Defense Advanced Research Projects Agency, N66001-97-1-8906

This is an exploratory research project on advancing the performance of silicon-based field effect transistors. The utilization of shallow metal silicide Schottky source/drain and the use of strained Si/SiGe materials are two of the pathways being explored to realize ultrasmall (~ 25 nm) channel silicon-based heterojunction electronics capable of low power and terabit operation. This is a collaborative effort with IBM Corp. and Yale University.

^ Silicon-Germanium Modulation-doped Field Effect Transistors
I. Adesida,* K. Ismail*
National Science Foundation, ECS 97-10418

This collaborative program with IBM Corp. is intended to significantly advance the growth and fabrication technologies for SiGe/Si modulation-doped field effect transistors (MODFETs) needed for low-power, high-speed microwave and digital applications. Specific goals are to study the physics of short gate-length p-type, n-type, and complementary MODFETs and to demonstrate simple circuits.

^ Ultra-High-Power GaN Power Amplifier at X-Band
I. Adesida,* W. Lu, D. Selvanathan
Air Force; TRW Corporation

This collaborative project with TRW Corporation is to fabricate an ultra-high- power GaN-based HFET amplifier on SiC at X-Band. Various processing techniques for GaN will be developed as part of this project

^ Metal Silicide Source/Drain MOSFETs for Nanoscale CMOS
J. Tucker,* C. Faulkner
U.S. Office of Naval Research, N00014-97-1-0588

Experimental MOS transistors are fabricated at ~25nm gate-length by substituting a metal silicide for highly doped silicon within the source and drain regions. The naturally formed Schottky barrier confines carriers in the "off" state, and gate-induced field emission causes tunneling into the silicon channel as the device is turned "on." PtSi is used for p-type and ErSi2 for n-type. Fabrication is greatly simplified, scaling is greatly improved, and most parasitics that plague conventional devices at sub-0.1μm dimensions are eliminated. The goal is ultrafast nanoscale CMOS with immunity to latch-up and single-event upsets, pursued as part of the silicon heterojunction terabit electronics effort.


Summary of Engineering Research