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Electrical and Computer Engineering

Reliable and High-Performance Computing
^ Amalgam: a Clustered Programmable-Reconfigurable Processor
N. P. Carter,* J. Cook, S. Ferrera, D. Gottlieb, J. Walstrom, C. W. Wang
Office of Naval Research

The Amalgam processor integrates multiple programmable processors and blocks of reconfigurable logic on a single chip to deliver ASIC-like performance and high programmability. We are investigating techniques for on-chip communication, the design of reconfigurable logic for computing applications, and methods of compiling real-world programs to this architecture. Initial experiments have shown that Amalgam achieves speedups of up to 23x when compared to a single programmable processor.

^ Composable Processors
N. P. Carter,* I. Ayub, J. Manton
C2S2 DARPA/MARCO Center

The increasing effort required to implement a state-of-the-art integrated circuit is becoming a significant barrier to entry for many embedded applications. This project is developing reduced-effort design techniques based on a set of composable processor modules that can be tiled together to form application-specific processors. Current research efforts focus on the development of software techniques to automatically generate target architectures for applications and the integration of sensors and transmitters with computing resources.

^ Sharing the IMPACT ILP Compiler Technology with U.S. Researchers
J. C. Gyllenhaal,* S. Y. Hwu, R. Iyer, W. M. Hwu, B. C. Cheng, J. W. Sias, M. C. Merten
National Science Foundation, CCR 98-09404

The IMPACT compiler, with such advanced features as predicated compilation, instruction-level parallelism optimizations, compiler engineered speculation, profile-based optimizations, advanced machine description facilities, scheduling frameworks for resource-sensitive code optimizations, and pointer-based dependence analysis and tracking facility, has become a premier compiler technology base for major U.S. companies as well as academic researchers. This project's software and documentation will be released in several phases over two years. The end product will be a high quality, readily available compiler environment that supports a wide variety of advanced instruction-level parallel processing research.

^ Advanced Predicate-Domain Code Optimization
W. M Hwu,* J. W. Sias
Intel Corporation

The predicated representation, in which control is implemented via conditional execution of instructions rather than branches, presents two general categories of new optimization opportunities: the optimization of program decision logic and the optimization of computation code using predication. This project aims to reduce control overhead by extracting control expressions from predicated code, optimizing these expressions using Boolean minimization techniques, and re-expressing control using more efficient sequences of predicate defining instructions. In the second area, this project works toward a paradigm in which stores, branches, and loop boundaries can be reordered freely to achieve performance goals.

^ Architecture Support and Program Analysis for Computation Reuse
W. M. Hwu,* D. A. Connors, B. C. Cheng
Intel Corporation; National Science Foundation, CCR 98-09478

Modern executable programs exhibit large amounts of dynamic redundancy where instructions groups each will repeatedly generate a small number of relevant computation results. Dynamic redundancy cannot be optimized away with traditional compiler techniques that require each instruction group to generate only one, invariant value. The goal of this project is to develop a cost-effective architecture framework and enabling reuse of execution results from instructions that generate a small number of frequent values. This approach can potentially result in drastic reduction of energy consumption while improving performance of a wide range of applications.

^ Architecture and Compiler Techniques for Optimizing Memory Accesses
W. M. Hwu,* B. C. Cheng, E. M. Nystrom
National Science Foundation, CCR 96-29948/98-09478; Intel Corporation

The goal of this research is to develop an integrated compiler and architecture approach to drastically reduce the frequency and cost of memory accesses in future computer systems. In particular, a compiler strategy that is built upon interprocedural pointer analysis and new heuristics for estimating the probability of colliding pointer contents will be developed to take full advantage of the data speculation features in future microprocessors. The insights provided by fully disambiguated memory accesses may drastically change the future course of run-time data speculation supports.

^ Compiler and Architecture Support for Program Tunneling
W. M. Hwu,* M. T. Conte, M. C. Merten, A. R. Trick
Hewlett-Packard

Modern programming paradigms often impose major performance penalties on application programs. Object oriented programming, structured exception handling, automatic memory management, middleware services, and operating system calls are all examples of such costly features. The goal of this research is to eliminate the cost of these features for the frequently traversed paths of executable programs. Architecture support, in the form of new protection schemes and no-overhead profiling mechanisms, will be developed to enable the run-time optimizer to safely perform aggressive optimizations.

^ Deep Program Analysis
W. M. Hwu,* J. W. Sias, B. C. Cheng, E. M. Nystrom, H. C. Hunter
Intel Corporation; National Science Foundation 98-09478

Current code analysis techniques draw dependences based largely on program structure and on register and memory accesses, many of which are not inherent to algorithms but are merely side effects of implementation in a particular architecture or coding paradigm. The conservative nature of these analysis techniques limits the compiler's ability to perform broad, powerful code optimizations. Deep program analysis is intended to discern the fundamental algorithmic dependences of input programs from among those artificially imposed. The application of deep program analysis techniques could revolutionize program optimization and execution models, significantly boosting the performance–power ratio in future computer systems.

^ IMPACT Post-Link Optimization Framework
W. M. Hwu,* M. C. Merten, R. D. Barnes
Hewlett-Packard; Microsoft

Commercial software vendors distribute products in binary executable form, compiled for a specific processor. Very limited technology exists for optimizing binary executables, thus preventing end users from optimizing programs for their particular machines. To remedy this problem, researchers are developing a static binary optimization framework that will serve as a bridge between the binary executable and the IMPACT compiler. Using this framework, the team can implement both general and processor-specific optimizations and generate a new executable for the particular user's machine. Such optimization could be performed at the time of program installation or off-line, while the user's machine is idle.

^ The IMPACT Run-Time Optimization Framework
W. M Hwu,* M. C. Merten, A. R. Trick, R. D. Barnes, E. M. Nystrom, J. C. Gyllenhaal
Advanced Micro Devices; Microsoft

Aggressively optimizing applications for diverse workloads without causing code explosion is often an intractable problem. However, significant performance gain can be achieved through targeted optimization. To direct optimization efforts, it is critical to identify and optimize the execution hot spots for the current workload. Therefore, researchers are developing a framework for adaptive, run-time optimization. This framework includes efficient run-time optimization algorithms, techniques for identifying optimization candidates using nonintrusive profiling, and seamless deployment of optimized code. This framework will allow profiling and optimization of the application for the current workload even across dynamically-linked libraries.

^ Java Run-Time Architecture
W. M Hwu,* M. T. Conte, H. S. Kim
Hewlett-Packard

This project focuses on enhancements needed to create highly optimized native code for dynamic Java server applications. This includes the construction of a next-generation Java run-time prototype that includes a means of integration between dynamic code production and static code reuse. Also included are a streamlined object model, non-intrusive profiling, dynamic optimizations, reduced inter-module communication overhead, run-time deployment of optimized code, improved memory management subsystem, and hardware enhancements to support Java specific features.

^ Memory-Efficient EPIC Processors
W. M. Hwu,* N. Carter
Semiconductor Research Corporation

Researchers are developing an improved EPIC architecture that will provide the high performance required by upcoming embedded applications while significantly reducing power consumption and memory bandwidth requirements. This architecture divides the processing resources of the chip into four independent clusters, with each cluster having its own program-controllable data memory. A decoded instruction buffer in each cluster reduces instruction fetch bandwidth and power consumption in loops. Compiler techniques are being developed to coordinate inter-cluster data movement to eliminate many of the memory accesses required during the execution of media programs on conventional architectures.

^ Native Compilation Technology for Java Bytecode
W. M. Hwu,* A. R. Trick, M. T. Conte, A. C. H. Hsieh, J. C. Gyllenhaal
Hewlett-Packard Co.; Intel Corp.

Maximizing the cost-performance potential of Java for low-cost applications requires compiling and optimizing them for the architecture of the target machine. Java's highly modular and dynamic nature presents a challenge to traditional static compiler approaches. This project combines the high-level program information contained in Java bytecode with a precise knowledge of the host machine's attributes, to design a compilation path producing highly optimized code. Furthermore, the native code version created is able to interact with a Java run-time and contains access points allowing the dynamic loading and linking of modules.

^ On-Chip Stable Storage Systems
W. M. Hwu,* S. Patel
MARCO/DARPA (part of MARCO Soft Systems Thrust)

The objective of the project is to develop fundamental software, systems, and circuit techniques to provide fast, reliable, on-chip storage to future nanoscale systems. The focus is on MEMS-based storage, which has the potential for bringing about dramatic improvements in performance, efficiency, and security. System architects and circuit designers jointly develop magnetic probe tip component models and a high-level simulation framework for mass data storage systems. The LZW compression scheme is optimized to take advantage of the longer read/write times of MEMES drives, and a complete logical design for a next-generation compression engine is developed.

^ Predicate Analysis and Predicate-Aware Dataflow Analysis
W. M Hwu,* J. W. Sias
Intel Corporation

Efficient and accurate analysis of predicate relationships and predicate-aware dataflow analysis are essential to effective optimization and scheduling of predicated code. A predicate analysis engine must first quickly analyze the code at the function level to determine all relationships among predicates. Then, it must store its findings in a database which can accurately and efficiently answer queries about the relations among predicates. The first objective of this project is to create a function level, accurate, and efficient predicate analysis engine. The second objective of this project is to create a predicate-aware dataflow analysis engine which is both accurate and fast.

^ Rapid Customization of Systems Software
W. M. Hwu,* S. Patel, R. Iyer
MARCO/DARPA (part of MARCO Center Soft Systems Thrust)

The objective of the project is to develop compiler-based, deep program analysis that transcends the boundaries currently separating the application, the dynamically linked libraries, and the operating system. Code-specialization of library functions and operating system services is based on interprocedural analysis of applications, programmatic logic analysis, data value analysis, and interthread escape analysis. Unnecessary code and modules are eliminated. A new fundamental model of the operating system functions, based on microkernel concepts, is developed to systematically verify the correctness of each customized version. Customization technologies are developed at the source and then at the binary level, with the long-term goal of handling commercial software. Potential benefits include rapid generation of software, smaller software footprints, reduced energy consumption, and higher performance.

^ Reliable Nanoscale Systems
W. M. Hwu,* S. Patel, N. Carter, R. Iyer
MARCO/DARPA (part of MARCO Center Soft Systems Thrust)

The objective is to develop architectural- and software-level mechanisms that provide a layer of robustness despite unreliable devices and potentially faulty applications. Both static and run-time approaches are pursued, due to their complementary capabilities in addressing reliability issues. On the static end, a hardware self-test during manufacturing allows a nanoscale chip system to detect and work around defects. Self-healing techniques and verification of interoperability are primary goals. On the run-time end, ARMOR-based fault-tolerant services using programmable hardware support are integrated into processing devices. Micro- and nano-checkpointing in the hardware and micro-checkpointing at the application level enable high-speed recovery. Customization of reliability mechanisms for each application are performed in connection with the Rapid Customization of Systems Software project.

^ Ubiquitous Instruction-Level Parallelism Architectures
W. M. Hwu, J. W. Sias, M. C. Merten, B. C. Cheng, D. A. Connors, R. D. Barnes, E. M. Nystrom, H. C. Hunter
Intel; Motorola; Microsoft; National Science Foundation 98-09478

As instruction-level parallelism (ILP) architectures such as Intel IA-64 and TI C6X move into the mainstream of computing, it has become critical to solve the technical problems involved in making these architectures appropriate for future embedded applications. The goal of this research is to develop new compiler, architecture, and microarchitecture concepts to drastically reduce the code size, data transfers, energy consumption, and die size of future ILP processors. New techniques will also be developed to further enhance the performance of future ILP microprocessors.

^ Value Analysis Compilation Framework
W. M. Hwu,* D. A. Connors, J. W. Sias
Intel Corp.

Analyzing the flow of values through program computation provides many opportunities for improving the performance of computer systems. This project has two related objectives: the optimization of existing control flow through value analysis and value speculation. Value flow analysis facilitates dead code elimination and control optimization. Value speculation refers to the execution of instructions before all source operand values have been determined. This can be done when instructions generate the same value for each execution, the same value for a high percentage of executions, or predictable values. Compilers can exploit these regularities through code specializations, collectively referred to as value speculation.

^ Verification of Run-time Optimized Code
W. M. Hwu,* M. T. Conte, J. W. Sias, M. C. Merten, A. R. Trick, R. D. Barnes
Hewlett-Packard

Executable programs are increasingly optimized and modified in the field. Just-in-time compilation of Java programs is a well-known example of such run-time code modification. The goal of this research is to overcome the technical challenges involved in automatic verification of run-time optimized code. An interdisciplinary approach that integrates program analysis algorithms and hardware test/verification techniques will be developed to cover a wide variety of software defects.

^ Adaptive Software-Implemented Fault Tolerance for Networked Systems
R. Iyer,* S. Bagchi, S. Chen
National Science Foundation, CCR 99-02026

This experimental study investigates development of a set of general-purpose, fault tolerance services in a networked environment. The focus is on designing a software-implemented fault tolerance (SIFT) layer that provides fault tolerance services to user applications, manages user processes across the network, provides rapid error detection, and initiates recovery from errors in the hardware, operating system, applications, and the SIFT layer itself. The SIFT layer protects all key components in a distributed system, including the components of the SIFT layer.

^ Creating a Foundation for Service Quality: Security, Performance, and Availability
R. Iyer,* J. Xu
Motorola, Inc.

The goal of this research is to investigate and to create a foundation for multidimensional (including fault tolerance, security, and performance) validation of the Service Quality of complex computing systems. To address this challenge, researchers study the complex nature and variety of unexpected conditions that can affect the system. They explore the interactions of system fault tolerance, security, and performance and their combined impact on the Service Quality delivered by the system. In order to fully stress the system (jointly and along each dimension) researchers explore the feasibility of developing comprehensive stress generators capable of generating faults and security attacks, variable-intensity workloads, and emulated errors or failures.

^ Design and Fault-Injection-Based Evaluation of Error Detection and Recovery in X2000 Testbed
R. Iyer*
Jet Propulsion Laboratory

The goal of this project is to develop a fault injection environment for evaluating the X2000 testbed with a focus on the communication module supporting the IEEE 1394 bus architecture. The approach is to build a local distributed testbed (consisting of at least three processing nodes) that runs the VxWorks operating system, supports the 1294 bus architecture, and contains a detection and recovery configuration sufficient to support automated fault injection. A framework (NFTAPE) is developed to conduct automated hardware and software fault injection experiments in this testbed to characterize the failure behavior of the 1394 architecture.

^ Design and Validation of High-Availability Networks
R. K. Iyer,* D. Ahuja, D. Stott, J. Zymla
Compaq Computer Corp.

This project focuses on the design and validation of reliable cluster computing systems. Issues include the reliability of switching technologies and the design and implementation of software environments to provide adaptive levels of fault tolerance. The design topics address methods for ensuring predictable dependability and responsiveness in network environments, including both homogeneous and heterogeneous systems. Validation topics include multidimensional validation of complex, high-performance, networked configurations that must deliver high-availability services under heterogeneous operating systems, computer platforms, and switching technologies.

^ Efficient Measurement and Validation of Networked Systems
R. K. Iyer*
Microsoft Corp.

This project focuses on understanding and preventing network failures. Two issues are addressed: the monitoring and measurement of network systems and the validation of these systems. Tools for collecting and analyzing failure data in a network environment are being developed to help in understanding network failure behavior and in locating the problem areas. Validation focuses on availability and performance perspectives. A fault-injection-based validation tool is being developed that incorporates a synthetic workload generator and is capable of injecting faults and testing on NT platforms. Platforms include single nodes running shadow disks or a RAID system, NT clustered platforms with recovery, and SMP clusters.

^ Fault-Injection-based Benchmarking
R. K. Iyer,* W. Gu, D. Stott, J. Zymla
Motorola, Inc.

Until now, fault injection tools have provided fault triggering, status and error logging, configuration, process management, and the actual fault injection in a single tool. The complexity of these fault injectors and their reliance on platform-specific features generally makes it difficult or impossible to conduct a variety of fault injection experiments on a single target, since each injector must be ported and configured individually for each experiment. The goal of this research is development of NFTAPE, a distributed test and evaluation tool with the following design objectives: use of a standard configuration process common to all fault injection experiments; placement of services common to most fault injectors in a single tool; and use of a simpler fault injector conforming to an API. NFTAPE provides flexibility in conducting fault injection and experimentation on a variety platforms.

^ Providing Technology for Evaluation of REE System and Application Software
R. K. Iyer,* K. Whisnant, P. Jones, C. Basile
Jet Propulsion Laboratory, NASAJPL 961345

Chameleon is an adaptive infrastructure that allows different levels of dependability requirements to be concurrently supported in a networked environment. Chameleon provides dependability through the use of special ARMORs (Adaptive, Reconfigurable, and Mobile Objects for Reliability), which control all operations in the Chameleon environment. The goals of this project are to continue development of Chameleon by extending its fault tolerance, implementing a communications interface, validating its fault tolerance using NFTAPE (a software-implemented fault injection environment), and using it for evaluation of the REE system and application software.

^ Future Communication Technology for Public Safety
L. Liu,* J. P. Monks, W. M. Hwu
Motorola

In the next decade, the communications technology for public safety officials will be revamped to take advantage of the capability of modern digital communication systems. It is, however, unlikely that current commercial digital communication schemes will be able to satisfy the stringent requirement of constant connection, very low power, congestion control, and ease of use. The goal of this project is to define the architecture of the public safety digital communication systems via careful analysis of field requirements and creation of new communication protocols. An interdisciplinary approach is taken to integrate user behavior studies with core technology development.

^ An Adaptive, High-Performance Software Infrastructure for Hierarchical Systems
S. Lumetta*
National Science Foundation, CISE/ACIR Career Award

Machines with deep memories now dominate supercomputing and provide most enterprise-level computing, making the successful development of a general-purpose approach to such platforms imperative. Researchers are developing a high-performance infrastructure for these systems through the construction of four key components: a virtual machine that abstracts resource allocation and management issues into a simple interface; a hierarchy-aware run-time system that offers the illusion of a non-hierarchical system by adapting to the current hierarchical virtual machine; language constructs and dynamic compiler support to tune application behavior; and applications that demonstrate the value of the framework.

^ Capacity Versus Robustness: A Tradeoff for Restoration in Mesh Networks
S. Lumetta,* S. Kim
Defense Advanced Research Projects Agency, MDA972-99-1-0005

Researchers are investigating capacity-efficient recovery methods in high-speed networks. The team recently demonstrated an extension of generalized loopback that operates on a subgraph of the full backup graph in an existing network. The backup capacity on remaining links can then be used to carry unprotected traffic, while all primary fibers retain failure protection. The results demonstrate robustness comparable or superior to that available with covers of rings while providing an additional unprotected traffic capacity of roughly 20% of the network's primary capacity.

^ Reliable, Efficient Communication on a Fast Ethernet Cluster
S. Lumetta,* J. Joh
University of Illinois, Campus Research Board

Networks of workstations (NOWs) have proven to be an inexpensive yet effective alternative to vendor-packaged parallel architectures. The performance of NOW's running on Fast Ethernet is often limited by TCP/IP communication overhead between the nodes in NOWs. Researchers are developing a new, lightweight, reliable communication protocol incorporating ideas of user-level communication, lightweight flow control, and multiple network interfaces per connection. The protocol supports the large body of existing parallel applications written to the Message Passing Interface standard. Researchers will evaluate the effectiveness of their design in terms of the performance of these applications when using their protocol.

^ Survivability and Reliability in Direct Access Networks
S. Lumetta,* L. Li
Defense Advanced Research Projects Agency, MDA972-99-1-0005

Researchers are developing routing and recovery protocols to provide reliable connectivity in direct access optical networks (DANs). DANs decouple access from routing, allowing new users to access to the network without incurring the high cost of an optical switch. Through this decoupling, researchers enable more cost-effective and reliable network expansion. Direct access also simplifies the models of ownership by reducing the depth of the ownership hierarchy and the number of potential security hazards and points of failure for a connection. Finally, DANs allow network providers to offer a wider variety of bandwidth and reliability options.

^ Measurement of Transient Errors in Microprocessors
J. Patel,* K. Wells, H. Kommaraju
Jet Propulsion Laboratory

This research addresses the measurement of error rates in commercial microprocessors. Microprocessors are core computing engines in the NASA Remote Exploration and Experimentation Project (REE). One serious problem is single-event upsets due to high intensity radiation in outer space. Knowledge of these error rates is essential in the design of the highly fault-tolerant REE computing systems. It is the measurement of these error rates that is the focus of the proposed research. The research will generate software tools that are capable of measuring and characterizing any errors in microprocessors.

^ VLSI Test
J. Patel,* A. Pandey
Semiconductor Research Corp.

The cost of test application of a single chip grows as a function of the number of clock cycles and/or number of storage bits required to test a chip. As a result, test application time and test data volume have become serious problems in testing of system-on-chip designs. In this research, new scan and BIST organizations are being devised that reduce not just data volume but also test time and associated hardware. Hybrid DFT techniques that combine BIST with deterministic scan vectors are also being investigated.

^ Design Verification of Pipelined Microprocessors
E. M. Rudnick,* M. Bose, L. Lai, D. Burke
Motorola Inc.; Semiconductor Research Corp.

This research involves architectural verification of pipelined microprocessors using a simulation-based methodology. Biased random instruction generators are commonly used to provide tests for simulation, but generation of adequate test sequences to uncover all design errors continues to be a problem. The goal of this research is to develop techniques to improve the quality of tests generated by a biased random instruction generator so that the tests cover design errors that are likely to occur. A genetic algorithm framework and deterministic procedures are being developed for this purpose, and experiments are being conducted using the PowerPC and ARM7 architectures.

^ Distributed Object Integration for the Quorum Program
W. H. Sanders,* M. Cukier, S. Krishnamurthy, J. Ren, M. Seri
Defense Advanced Research Projects Agency, subcontracted from BBN Technologies

The purpose of this work is to advance the development of the AQuA architecture, whose goal is to provide adaptive fault tolerance to distributed applications via commercial off-the-shelf hardware and operating systems. The AQuA architecture allows application programmers to request desired levels of dependability during run-times of applications. It also provides adaptive fault tolerance. In distributed systems, resources change dynamically, and different types of faults can occur anywhere and anytime. AQuA is designed to provide dependability for CORBA applications. It provides fault-tolerance mechanisms to ensure that a CORBA client can obtain reliable services, even if the CORBA server object that provides the desired services suffers from crash failures and value faults.

^ ITR: Experimental Validation of Large-Scale Networked Software Systems
W. H. Sanders,* W. M. Hwu, S. S. Lumetta, R. K. Iyer, B. Brothers, S. Chen, M. Conte, K. R. Joshi, Z. Kalbarczyk, R. Lefever, J. Matarazzo, J. Sias, H. Zhang, J. Zymla
National Science Foundation, Information Technology Research Program, contract 0086096

The validation of networked computing systems is challenging due to the complexity of these systems and the diversity of their components. The adaptability requirements of such systems create additional problems for validation. The objective of this project is to develop the theory, methodology, and tools necessary to analyze and validate a complete networked application and system for its reliability, performance, and security. The research is performed at code, node, and network levels, developing techniques to validate the system at each level and studying how the validation results at one level can be used as input to the validation process at higher levels.

^ Intrusion Tolerance by Unpredictable Adaptation (ITUA)
W. H. Sanders,* M. Cukier, P. J. Lyons, P. Pandey, H. V. Ramasamy
Defense Advanced Research Projects Agency, subcontracted from BBN Technologies

The goal of this project is to develop middleware-based intrusion tolerance techniques that help applications tolerate (that is, continue to function without violating program and data integrity) a class of attacks. Researchers are investigating planned attacks that are carried out in multiple phases in a coordinated manner, focusing on the impacts they have on system resources. Researchers are developing algorithms and software tools that will allow applications to adapt to the effects of such attacks. This approach builds upon adaptive middleware technology that enables applications to be aware of and responsive to the availability and quality of system resources.

^ Motorola Center for High-Availability System Validation
W. H. Sanders,* G. Clark, T. Courtney, D. Daly, D. Deavours, S. Derisavi, P. Webster
Motorola, Inc.

The Motorola Center, which operates under the umbrella of the Motorola Communications Center, was established in December 1999. Researchers are developing new theory, algorithms, and tools to predict the availability of computer hardware, software, network, and telecommunication systems. In particular, research is focused on providing the theory and tools to evaluate, via model-based methods, whether a particular design meets its availability, reliability, or performance requirements. Benefits to the center sponsor include a corporate-wide license of the UltraSAN and Moebius modeling packages, as well as the ability to consult with center researchers.

^ Survivability of Large-Scale Information Systems
W. H. Sanders,* M. Cukier, S. Krishnamurthy, J. Ren, M. Seri
Defense Advanced Research Projects Agency, subcontracted from BBN Technologies

This work provides a methodology for specifying the survivability that an application desires in terms of the quality of service delivered to it, and for specifying mechanisms and policies that can be used to achieve the desired survivability, in terms of the specified measures. Choices of policies and mechanisms are not easy, and it is not usually obvious how a change in resources will translate to a change in survivability. Researchers provide a method to specify the desired survivability and a specification of what information must be collected to make adaptation decisions, and they implement several mechanisms that can aid in building a survivable system.


Summary of Engineering Research