^ Logic Synthesizers for VLSI Chip Design S. Muroga,* V. Jayasena, Y. Luo, Y. Nakano, Y. Wang University of Illinois
Automated design of logic networks for VLSI chips is indispensable for designing powerful processor chips. Although logic networks have been designed without loops for combinational functions, this research team found systematic algorithms for designing networks with loops, using no more logic gates or interconnections. In addition to this project, research continues on a new synthesizer of logic networks with minimum delay or area for engineering changes where a logic network is interactively modified for the adjustment of delay time or area as a logic network is laid out. For this purpose, researchers are developing new algorithms and extending the transduction method.
