This project considers the problem of design error detection in logic design implementations. Techniques have been developed to detect and automatically correct single and multiple design errors. The approach relies on functional verification methods based on generating binary decision diagram (BDD) representations of logic equations at output nodes of a gate level implementation of a design and comparing them with functional specification. It also uses Boolean equation formulation and solution in locating and correcting errors. The techniques can also be used in diagnosis and in design modification at the gate level.

The aim of this research is to develop numerical methods and computer algorithms for design verification and testing of VLSI circuits at the timing and logic levels. This work includes circuit extraction from layout and automatic test generation for bridging faults. Hierarchical and mixed-mode simulation methods are being developed as well as RF analog circuits.

Our goal is to develop computer-aided design techniques for predicting the reliability of VLSI circuit designs caused by electromigration effects, to detect if and when the design does not meet reliability specifications, and to recommend changes in the design to meet these specifications. Electromigration is a major reliability problem and is becoming increasingly critical. Traditional worst-case approaches to electromigration estimation may produce unreasonably pessimistic results. In our work, we have derived statistical techniques that allow design for reliability to be done at a reasonable cost. The results also give an estimate of the average power drawn by different parts of the design. Fast methods for estimating worst-case voltage drop in the power bus are being studied.

The aim of this project is to develop accurate component models and simulation programs that are essential for the analysis and development of optoelectronic integrated circuits, optical interconnects, and buses. Circuit models for opto electronic devices, such as MSM photodetectors, both edge- and surface-emitting multiple quantum-well laser diodes, and waveguides, have been developed and implemented into a simulation circuit-level program, ;gnSPICE. High-speed photoreceivers and transmitters are being investigated for both monolithic and hybrid integration. Also, optical link simulator iFROST has been developed for systems-level analysis of parallel optical buses in high-performance computing and communcation systems.

A fully functional systems testbed is used to develop optoelectronic subsystems such as optoelectronic transmitter arrays, photoreceiver arrays, and switching subsystems. Operating systems and softwares are also being developed for multimedia, video/audio teleconferencing over optically linked workstations in the Beckman Institute and the Digital Computer Laboratory, which is over 1 km away, and also to other users of AT&T's experimental university network nationwide. Recently 1 Gbps trunk ported has been implemented using UIUC optoelectronic devices.

Designing reliability into VLSI to obtain first-pass reliable VLSI devices has become increasingly important in recent years. Both long-term and catastrophic early life failures will be modeled and simulated to study VLSI reliability. For the simulation of circuit performance degradation, new MOS transistor models that include hot carrier-induced device degradation effects and electrical overstress have been developed. Both experimental and theoretical investigations are pursued for development of new models and simulators. Simulation capability is being verified using industry data.

Asynchronous transfer mode (ATM) networks are used to provide high bandwidth for future information infrastructure. The scalability of ATM switches and queueing modules is being investigated to maximize the utility of photonic, electronic, and optoelectronic devices for multimedia applications. New algorithms for switch control, input queueing, and priority control are being developed and tested on an iPOINT testbed using multimedia traffic and its model.

State-of-the-art VLSI chips are being used in portable systems that require compactness, high speed, and long battery life. New innovative circuit design techniques are required for high speed with low power consumption. Power-minimum design optimization methods are being developed to drastically reduce the power consumption of state-of-the-art CMOS circuits. Several benchmark circuits such as multipliers are used to demonstrate significant power savings without resorting to power supply sealing, substrate biasing, or thresh voltage turning.

The interconnects for high-speed circuits and systems need to be modeled accurately in order to examine the crosstalks and signal propagation delay times. In this project, we are developing new modeling and simulation techniques for time-efficient and yet accurate simulation of interconnect lines in conjunction with fast MOS timing simulator ILLIADS. In particular, the interface issues between Ricatti solver and the method of moment for transmission line analysis are being investigated for time-efficient and accurate timing simulation of very large digital integrated circuits.

We plan to develop the scientific and engineering expertise needed to produce reliable deep submicron, low-power integrated circuits and to develop I/O protection circuits with electrical overstress (EOS) and electrostatic discharge (ESD) resilience. We are also exploring the physics of device operation under short duration, high current stress, and at high temperature. We are developing models and guidelines for reliable I/O protection circuits for both bulk and silicon-on-insulator (SOI) CMOS technologies. We will also develop design methods to ensure that on-chip interconnects have electromigration resilience while consuming a minimum of chip area. To evaluate the current stress levels in large-scale metallic interconnects, we are developing efficient statistical techniques.

Electromigration and the interconnect parasitic resistance increase are thermally activated; therefore, intercon nect temperature must be correctly modeled in order to predict (simulate) electromigration reliability and electrical performance. Circuit design with the aid of accurate reliability simulation tools is far preferable to blind application of overly conservative reliability design rules, which generally result in significant area and performance penalties.

We are developing accurate temperature models for interconnects, which account for joule heating, heat flow from the substrate, and heat flow from neighboring interconnects. A three-dimensional, geometry conserving layout extractor has been developed. Temperature models have been implemented in temperature-dependent timing simulator ILLIADS-T.

Excessive power dissipation in ICs discourages their use in portable equipment and causes overheating, which can lead to soft errors or permanent damage. The main conceptual difficulty in power estimation is that the power depends on the input signals driving the circuit, a more active circuit will consume more power. To account for this, most recently proposed power estimation methods are based on a probabilistic approach, but are limited to combinational circuits. The aim of this project is to handle large VLSI circuits, allowing for sequential and other circuit architectures. We handle sequential behavior by using statistical estimation techniques to measure the latch output statistics. From the results, it is possible to compute the total power.

The high density of modern integrated circuits has led to unacceptably high levels of chip power consumption. Because of limited battery life, this presents a severe limitation in the design of portable or mobile electronics. Even in line-powered equipment, high-power chips require expensive packages and heat-sinks. We are developing power estimation techniques that work at high levels of abstraction, so that the power can be estimated even before the gate-level design description is available.

Power estimation from a high-level of abstraction is important in order to provide early warning of major power problems. If part of the chip is reused from a previous design, then the internal details of that part are known. It would be very efficient to have a ``high-level'' model of the power dissipation for this part, a ``macromodeling for power'' technique. At the lowest level of abstraction, this is a problem of ``library characterization'' for power, where one is trying to model with as much detail as possible the power dissipation of a transistor-level cell representation by a gate-level power model. At the next level, we want to extend this macromodeling technique to larger cells or, in general, any combinational block specified at the gate or lower level.

We are developing a methodology for designing reliable ICs which would allow designers to do reliability prediction and reliability budgeting. Under reliability prediction, the system will accept a description of the design at either a gate or higher level and will provide an estimate of the chip reliability. Under reliability budgeting, a specified failure rate or MTF for the whole chip will be partitioned among the different chip components to provide reliability targets for smaller pieces of the design. This allows designers to use less conservative design styles, thus requiring less silicon area and improving chip density and performance without sacrificing overall chip reliability.

In order to control the power dissipation in modern VLSI circuits, parts of the design that are not required to compute for a certain time period are put in sleep (idle) mode by enabling a sleep signal. The power supply to these parts is maintained, but the clock driving them is disabled, so that circuits in sleep mode will dissipate leakage current. In modern and future low-Vt CMOS circuits, the leakage consists primarily of the MOS subthreshold conduction current. We are developing logic design techniques that aim to reduce the leakage current during sleep mode.

The reliability implications of scaling gate oxide thickness below 10 nm are being investigated. In logic circuits, reliability is limited by defect-related breakdown. Accurate and verifiable models for time-to-breakdown must be developed. In nonvolatile memory circuits, oxide degradation is the critical reliability issue. Oxide degradation is manifest as charge trapping in the oxide, which impacts the erase time, and as leakage current, which reduces the data retention time. We are presently investigating the physi- cal basis for stress-induced leakage current and quantify- ing its dependencies on oxide thickness and stress (erase) conditions.

The goal of this project is to develop a hierarchical reliability-driven CAD system for concurrent checking of performance and reliability during the design of deep-submicron VLSI/VLSI circuits. At the top of the hierarchy lies reliability design rule checking. We are developing design verification capabilities against hot-carrier-induced degradation, time-dependent dielectric breakdown, electromigration, and electrostatic discharge/electrical overstress. Below rule checking in the design hierarchy are timing and circuit simulation. The timing and circuit simulator ILLIADS-R and JETSIM are enhanced to simulate circuit reliability in addition to performance. A user-friendly interface is being developed for remote uses across the Internet or in a group environment.

Increased power yields higher operating temperatures which, in turn, impact the performance of the circuit. Circuit-level electrothermal simulation is not a feasible tool for studying VLSI-size circuits. This project involves adding temperature models to a timing-level simulator that can handle VLSI circuits. The circuit is partitioned into blocks. Power consumption for each block is calculated, and then the chipwide temperature distribution is constructed. Once the temperature distribution is known, device models are adjusted to local temperatures, and the timing simulator is used to study chipwide performance.

Silicon-on-insulator CMOS technology holds great promise as an improved substrate for low-power, high-speed integrated circuits. However, SOI-CMOS ICs will not be produced on any large scale if they are susceptible to electrostatic discharge (ESD) induced failures. This project will answer the fundamental questions about the ESD reliability of SOI-CMOS technology. Thermal modeling, design of protection devices, and experimental testing form the basis of this investigation. Device models and stress limits developed in this research project will be implemented in a CAD tool for full-chip ESD reliability verification.

This project is concerned with the development of a mixed-mode simulator called iSPLICE3 for the simulation of MOS and bipolar mixed analog-digital circuits. A mixed-mode simulator allows the circuit designer to intelligently trade off simulation accuracy for speed within the scope of a single simulator. The program uses electrical, switch-level, and logic analysis techniques based on event-driven simulation. The current objective is to investigate automatic partitioning methods using iSPLIT to convert transistor level circuits into higher level descriptions, and to perform benchmarks with commercially available mixed-mode simulators.

This project explores various methods of parallelizing circuit simulation. Both relaxation techniques and direct methods are considered. Of particular interest are the cluster-based architectures such as the CEDAR machine designed at the University of Illinois in the Center for Supercomputing Research and Development. A hybrid/hierarchical scheme has been developed for this machine. Portability aspects are also being investigated on a variety of other emerging architectures.

The goal of this project is to develop new approaches for the analysis of switched-capacitor circuits, ;gS;gD modulators, and phase-locked loops. A multilevel simulator that uses a combination of continuous-time and discrete-time analysis techniques is being implemented for this purpose. The simulator allows behavioral, macromodel, and circuit-level descriptions to be used. New primitives are added using an analog hardware description language (AHDL) and macromodels are tuned using an efficient optimization technique.

High-resolution ADCs, when limited by component mismatch or circuit nonidealities, have relied on corrective measures such as trimming or electronic calibration. Two key concepts explored are dithering and nonlinear interpolation, which are to corrupt the signal with a known dither and to subtract the dither digitally later. Since the calibration dither voltage injected into a specific stage experiences a path gain set by a capacitor ratio, the capacitor ratio error of the path can be measured indirectly by measuring its dither gain. The ultimate goal of this project is to maintain high-frequency performance by adding real-time trimming circuits operating in background and leaving fast original architectures intact.

Frequency synthesizers for communication receivers demand a very low-jitter performance of a high-Q VCO because the reference frequency of the PLL is usually the channel spacing. Because of the phase detection at this low freqiency, the PLL loop doesn't effectively suppress the phase jitter of the VCO. This research is to explore the feasibility of using an integrated ring-oscillator VCO for frequency synthesizer applications. The high level of the VCO phase jitter will be suppressed by the PLL loop gain by using a phase detector operating at much higher frequencies than the channel spacing. The jitter generated by the fractional-N divider will be whitened, either using a sigma-delta or a randomizing technique.

New digital video applications have created a need for low-voltage/power NTSC decoder with digital outputs for portable applications. NTSC decoders are being implemented digitally with front-end ADCs. Although the current approach is sound and flexible due to its digital-domain implementation, it suffers from the large chip area and power consumption. We propose to determine the feasibility of implementing the same function with less chip area and power with lower supply voltage. For this, we will investigate the feasibility of partitioning the NTSC decoder system for a mixed analog/digital implementation with more analog functions incorporated. For TV audio, a completely digital FM demodulator is being developed.

A demand for digital signal processing has grown rapidly in the high-quality video reproduction areas such as multimedia and high-defintion television. Existing monolithic flash-type ADCs for video purposes, although very fast, have been limited to typical 8-bit applications, and require excessive area and power. The proposed research will be focused on the application of scaled CMOS technologies to low-voltage 10-bit video-rate data conversions. The goal of the research is to develop and prototype a 10-bit CMOS video ADC using a single 3-V supply and 25 mW. A substantial power savings is obtained not by efficient de- signs but by efficient architectures, such as recycling of amps, capacitive reference dividers, and purely dynamic comparators.

An FM demodulator is being implemented digitally in software using a quadricorrelator algorithm to make it compatible with future digital wireless and FM receiver systems. The proposed digital FM demod ulator uses a sinc-cube decimation filter with its first zero either on the alternate or on the adjacent channels for high channel selectivity, a digital differentiator using a three-point approximation for frequency discrimination, and a digital division for AM rejection. A bitstream FM signal from a fourth-order bandpass delta-sigma modulator is FM-demodulated to exhibit a SNDR of 71 dB, a THD of 0.01%, and an AM rejection of 77 dB in simulations using a signal band limited to 1/200 of the sampling frequency and amplitude-modulated with a modulation index of 0.9 (90% AM).

New PCN/PCS systems have created a demand for low-power, robust communications transceiver designs. These systems typically rely on low-rate, frequency-hopping, spread-spectrum techniques to provide multiple access capability with FSK modulation applied to the data. Low data rates, susceptibility to interference, and distortion via fading channels are all characteristics of these systems. The proposed research will examine CMOS designs of fast-hopping transceivers with wavelet modulation of the data. The goals of this project include increased data rates and improved immunity to interference and fading channels employing low-power architectures suitable for use in portable, battery-powered communications devices.

This research focuses on the development of low-power adaptive equalizers via the application of algorithm transformation techniques. In particular, we have employed a class of algorithm transformations known as algebraic transformations at the algorithmic level in order to obtain low-power adaptive filter architectures. Algorithmic performance of these equalizers as a function of power savings is being studied in asynchronous transfer mode (ATM) local area networks (LANs) and very-high-speed digital subscriber loops (VDSL). Finally, VLSI implementation of one or more of these architectures will also be undertaken.

Power dissipation has become a critical design concern in recent years because of the emergence of mobile applications and as well as concerns about reliability and packaging costs. In this research, we have developed an analytical methodology for estimating signal transition activity from its word-level statistics. These statistics can then be propagated throughout a given architecture, and its total transition activity can thus be computed. This methodology will be built into a CAD tool to allow the system designer to explore the design space and synthesize low-power DSP hardware.

The goal of this research is to develop an information-theoretic basis for VLSI computation, to determine fun damental achievable bounds on VLSI performance, and to investigate methods to achieve these bounds. We have developed a mathematical basis for power reduction in VLSI systems in which the computation in a DSP algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement. Architectures implementing a given algorithm are equivalent to communication networks each with a certain capacity. Numerical calculations of lower bounds on power dissipation for simple static CMOS circuits as well as pipelined and parallel processing architectures have demonstrated the usefulness of the proposed framework.